Field of the Invention
The invention relates to a digital/analog converter with a weighted capacitive converter network.
Capacitive digital/analog converters have long been known, for instance from the book by D. Seitzer, entitled "Elektronische Analog-Digital-Umsetzer" [Electronic Analog/Digital Converters], Springer-Verlag, Berlin, 1977, pp. 82 ff. A switch controlled by digital information charges a capacitor in a first clock period. During a second clock period, the switch is opened and through a further switch a further capacitor is connected is parallel, so that the charge stored in the first clock period is distributed to the two capacitors. A switch network and a weighted capacitive network can substitute for the switch and the capacitor. The basic principles of weighted networks for D/A converters are known, for instance from the book by U. Tietze and Ch. Schenk, entitled "Halbleiter-Schaltungstechnik" [Semiconductor Circuitry], Springer-Verlag, Berlin, 7th Edition, 1985, pp. 739 ff.
A D/A converter according to the principle of charge redistribution with a weighted capacitive network is followed, in certain applications, by a time-continuous interpolation filter, in other words a low-pass filter. Due to the time-continuous filter, the output voltage of the digital/analog converter becomes time-continuous, or in other words is weighted at all times. Therefore, the transient response of the converter has a considerable influence on the attainable converter outcome. The goal in principle, in the conversion of one and the same digital code, is to obtain, at the output of the time-continuous filter, an analog value that is precisely equivalent to the digital code.
In practice, however, the output voltage associated with a digital code may be adulterated by switching peaks of the converter switch, as will be explained below in conjunction with the drawings. In such a converter, that phenomenon of switching peaks is especially disturbing at transitions from one code to the next, whenever several or many elements of the code change.
Although it is difficult in principle to avoid non-linearities entirely, a characteristic curve with a form that enables good linearity is desirable.
The use of an unsplit capacitive network requires larger capacitors to be used, which in turn results in a dramatic increase in the chip area required.
Shortening the transient response time causes the time in which a disturbed signal is present to be minimized, although that requires substantially more capacity than the corresponding original conversion system. That route is in fact not achievable especially in high-speed converters.
Although it is also possible for the D/A converter and the following filter to be followed by a sample and hold element, which samples the command value of the converter and keeps it constant during the time when switching peaks can occur, in order to improve the linearity performance, that option entails considerable expenditure for circuitry because the sample and hold element must be integrated with the rest.